1. Field of the Invention
The invention relates to semiconductor memory and in particular to a split gate memory cell and a fabrication method thereof.
2. Description of the Related Art
Semiconductor memory devices commonly take various forms, such as EPROMs, EEPROMs, and flash memory devices. Currently, flash memory, such as a split gate flash memory is widely applied in large capacity non-volatile memory technology. Typically, the split gate flash memory includes a split gate structure having a floating gate for charge storage and a control gate to control the charge storage. The split gate structure may further include a thin gate dielectric or tunnel oxide film formed between the floating gate and the substrate and an intermediate dielectric film formed between the floating gate and the control gate.
FIG. 3 is a cross section of a conventional split gate memory cell. The split gate memory cell includes a semiconductor substrate 300. A polysilicon floating gate 306 is disposed on the substrate 300 and insulated therefrom by a gate dielectric layer 304. A polysilicon control gate (i.e. word line) 312 is laterally adjacent to the floating gate 306 and insulated therefrom by an interpoly dielectric layer 310 and a thicker cap oxide layer 308 formed by local oxidation of silicon (LOCOS). A source region 301 and a drain region 303 are formed in the substrate 300 on both sides of the split gate structure.
To integrate the split gate memory cells on a chip with the peripheral circuits, additional lithography steps are required. Each additional lithography step requires a respective different mask or reticule, with the cost of masks for lithography high.
Thus, there exists a need in the art for an improved split gate memory cell with fewer lithography steps during manufacture of split gate memory cells.